The present invention relates generally to semiconductor devices and semiconductor manufacturing. More particularly, the present invention relates to an improved process for high-performance sub-micron CMOS technologies as may be found in high-performance logic applications such as state-of-the-art microprocessors or embedded DRAM implementations.
The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon die or chips. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
Metal-oxide-semiconductor (MOS) transistors, including the combining of n-channel and p-channel transistors as required for complimentary MOS (CMOS) technology, have been widely used to increase the density and performance of silicon-based electronic devices. CMOS technology has found its way into a wide variety of semiconductor device types, including microprocessors, various other logic applications and high density commodity DRAMs. By the late 1990s, each of these applications have had the common characteristic of very small, submicron (e.g., 0.18 to 0.35 micron) minimum features sizes. These logic applications and high density commodity DRAMs also exhibited a variety of significant structural differences.
For example, high performance logic device technologies: have reached minimum feature sizes (referring to transistor length values as measured across the gate electrode) in the 0.18 micron to 0.25 micron range; have applied four to six levels of metal interconnect; have used dual-doped gate electrodes (p+ polysilicon for p-channel and n+ polysilicon for n-channel transistors, sometimes referred to as dual-poly or dual-gate technology) in order to aid downward scaling and to help force each transistor type into the surface channel mode; have replaced the older LOCOS-based isolation process with shallow trench isolation (STI) giving much flatter surfaces and better control of the transistor width dimension; have successfully scaled the gate oxide to a range between 45 Angstroms and 65 Angstroms; and have formed silicides (usually titanium based) on the source/drain areas and polysilicon gate electrodes, using the well-known salicide process, thereby reducing lower-level interconnect RC delays.
The many levels of upper-level interconnect in such logic technologies have been separated by thick dielectrics, reducing capacitive coupling. This has required high aspect ratio vias filled with tungsten plugs which have been typically formed using a CVD tungsten process. But the tungsten plug contacts to substrate are not self aligned contacts (SAC). Extensive use of chemical mechanical polishing (CMP) has been used to provide the necessary planarization. This high performance technology has yielded logic products operating at clock rates of 250 MHz and higher.
In contrast, DRAM technologies have concentrated primarily on reducing the size of the capacitor associated with the MOSFET transistor used in connection with the capacitor memory cell, and has looked quite different from state-of-the-art high performance logic technologies. For example, since the memory cell has little tolerance for PN junction leakage, salicides are typically not used. The gate electrodes are typically polycides, using WSi2, with a cap oxide or nitride as is needed to form a self-aligned contact (SAC).
An important part of DRAM implementations is providing a low resistance word line for accessing memory cell data. For this reason, polycides have been used where the silicide may be somewhat thicker than that normally found in salicides. In some DRAM implementations, such as the illustrated example addressed above, a polysilicon landing-pad SAC is formed right up against the insulated gate electrode. The relatively thick dielectric spacer and cap oxide prevents shorting.
Due to its strict requirement to minimize leakage, DRAM has been late in implementing STI (shallow trench isolation) and, rather, has stayed with the older and well-characterized LOCOS-based isolation process. DRAM processes have typically formed no more than two levels of metal interconnect.
DRAM technology also typically uses thicker gate oxides since word line voltages may be boosted. Attainment of extremely robust transistors, using very thin gate oxides, is less important to DRAM technology. More important concerns have been high yield, high density, and long-term reliability. Thus, DRAM performance, as measured by clock rates, is usually significantly less than high performance logic implementations.
The typical DRAM capacitor is used in a variety of forms, with the stacked polysilicon-type dominating. DRAMs generally have not used dual-doped gate electrodes.
There is a recognized need to combine DRAM and high performance logic processes into what is generally referred to as embedded DRAM. To use the typical high density DRAM cell in the logic process, a self-aligned contact is needed. But the salicide process, as required for high performance logic, does not readily tolerate a thick cap oxide; its presence, of course, precludes the necessary interdiffusion of titanium or other refractory metal with the exposed polysilicon gate electrodes. On the other hand, a salicide process may be applied to the source/drain regions if the gate electrode is already provided with a silicide and is covered with a protective oxide or nitride film.
In view of the above and in connection with the present invention, it has been recognized that an advantageous gate electrode structure would offer dual-gate (p+ and n+ poly) capability, high conductivity like that of conventional polycides, cap oxides or nitrides and other more robust edge insulation, such that a self-aligned contact may be placed against this electrode, and improved thermal stability such that high temperature dopant activation anneals may be performed without excessive dopant migration into the overlying silicide. It is well known that dopants have very high diffusion rates in silicides as compared to polysilicon.
One approach to the dopant diffusion problem is to place a conductive barrier layer between the doped polysilicon and the overlying silicide. In a specific implementation of this type, a polycide gate structure includes a TiN barrier between layers of polysilicon and TiSi2. It has been reported, however, that upon reoxidation, the TiN barrier converts to TiO creating high contact resistance between the silicide and the underlying polysilicon. For further information concerning such efforts, reference may be made to xe2x80x9cIdentification of Gate Electrode Discontinuities, in Submicron CMOS Technologies, and effect on Circuit Performancexe2x80x9d, Keith A. Jenkins, et al., IEEE Trans. Electron Dev., v.43, May 1996, p.759. See also xe2x80x9cHighly Reliable W/TiN/pn-poly-Si Gate DMOS Technology with Simultaneous Gate and Source/Drain Doping Process,xe2x80x9d Hitoski Wakabayashi et al., 1996 IEDM, p.447; and xe2x80x9cW/WNx/Poly-Si Gate Technology for Future High Speed Deep Submicron DMOS LSIs,xe2x80x9d K. Kasai, et al., 1994 IEDM, p.497; and xe2x80x9cA Novel 0.15am CMOS Technology using W/WN,/Polysilicon Gate Electrode and Ti Silicided Source/Drain Diffusions,xe2x80x9d M. T. Takagi, et al., 1996 IEDM, p.455. Each of these references is incorporated herein by reference as background information to the present invention.
The present invention has a variety of uses including improved gate electrode processes and structures, and provides benefits including significantly greater tolerances to higher temperature annealing treatments. In addition, the present invention is useful in connection with the formation of self-aligned contacts as are needed for high density embedded DRAM applications.
The present invention is characterized and exemplified in a number of implementations and applications, some of which are summarized below.
According to one method embodiment, a polycide transistor gate electrode process involves a cap dielectric and dielectric spacer which exhibits a reduced diffusion transport of dopants between the underlying doped polysilicon and the overlying silicide. The reduced transport results from the presence of a thin barrier layer between said doped polysilicon layer and silicide layer, and the gate electrode process forms a thin polysilicon side-wall film against the polysilicon, barrier, silicide, and cap dielectric layers which is thermally oxidized. The polysilicon side-wall film is used for blocking substantial oxidation of the barrier film. The thin barrier film extends substantially across the doped polysilicon film and terminates close to said side-wall thermal oxide.
Another embodiment of the present invention involves a transistor gate electrode process comprising: forming an underlying polysilicon film and an overlying refractory metal nitride film, which is covered with a thin silicon nitride film which, in turn, is covered with a polysilicon film; forming, after photolithographic patterning a thin silicon nitride side-wall film against said polysilicon, refractory metal nitride, silicon nitride, and overlying polysilicon film; and forming lightly doped source and drain regions by ion implantation wherein the dopants penetrate said refractory metal nitride, silicon nitride and overlying polysilicon film and said penetrating dopants appropriately dope the underlying polysilicon film; and then oxidizing said overlying polysilicon film. The oxidized polysilicon film is again penetrated upon final n+ or p+ source/drain implants.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.